High speed multiplier design using Decomposition Logic
نویسندگان
چکیده
منابع مشابه
FPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic
The Baugh-Wooley algorithm is a well-known iterative algorithm for performing multiplication in digital signal processing applications. Decomposition logic is used with Baugh-Wooley algorithm to enhance the speed and to reduce the critical path delay. In this paper a high speed multiplier is designed and implemented using decomposition logic and Baugh-Wooley algorithm. The result is compared wi...
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ژورنال
عنوان ژورنال: Serbian Journal of Electrical Engineering
سال: 2009
ISSN: 1451-4869
DOI: 10.2298/sjee0901033r